In the manufacturing process of a nonvolatile semiconductor memory device typified by a NAND flash memory, dry etching technology is used in order to extend control gate electrodes in a specific direction and arrange floating gate electrodes (charge storage layers) below the control gate electrodes.
However, since the control gate electrode has a structure in which a metal-containing layer is stacked for the purpose of reducing parasitic resistance, metal contamination may be brought about in the nonvolatile semiconductor memory device after the metal-containing layer is processed by dry etching. For example, when the floating gate electrode is processed by dry etching, a phenomenon will occur in which due to sputtering etc., metal is scattered from the side surface of the metal-containing layer exposed at the side surface of the control gate portion for which processing has already been completed, and the metal adheres to the side surfaces of the IPD (inter-polysilicon dielectric) layer, the floating gate electrode, etc. of the nonvolatile semiconductor memory device, the vicinity of the tunnel insulating film, etc. Furthermore, when the metal components attached to the side surfaces etc. described above are removed using wet etching processing or the like in the post-processing after the dry etching processing, a phenomenon will occur in which metal components elute from the side surface of the metal-containing layer exposed at the side surface of the control gate electrode during the wet processing, and the metal components re-adhere to the side surfaces of the IPD layer, the floating gate electrode, etc. of the nonvolatile semiconductor memory device, the vicinity of the tunnel insulating film, etc.
To avoid the possibility of such phenomena, there is a method in which the side wall of the metal-containing layer is covered with a cover layer after the control gate electrode is processed by dry etching. However, in the case where an insulating film such as a silicon oxide film and a silicon nitride film is used as the cover layer, also the cover layer may be removed by etching when the IPD layer made of an insulating film is processed, and the side surface of the metal film may not be covered when the floating gate electrode is processed. In such a case, due to the removal of the cover layer, consequently metal contaminants may be released from the metal-containing layer. In the case where a semiconductor film such as an amorphous silicon film is used as the cover layer, when the cover film is not removed but left in the processing of the floating gate electrode, there is a problem that the semiconductor cover film will remain also on the side surface of the insulating film region above the control gate electrode, and a short circuit between control gates is likely to occur.